Module Details
Module Code: |
SYST C4602 |
Module Title:
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Digital Systems
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Title:
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Digital Systems
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Module Level:: |
8 |
Module Coordinator: |
Cathal Nolan
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Module Author:: |
Frank Fennelly
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Module Description: |
To provide learners with the knowledge and skills needed to design, simulate, synthesise and validate digital systems using SOC technology.
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Learning Outcomes |
On successful completion of this module the learner will be able to: |
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Learning Outcome Description |
LO1 |
Describe System on Chip (SoC) architectures and interfaces. |
LO2 |
Use contemporary Electronic Design Automation (EDA) tools to develop digital systems using field programmable SOC devices. |
LO3 |
Use a HDL to create a self-checking test bench to test a digital system which incorporates combinational and sequential logic. |
LO4 |
To use a SOC bus technology to interconnect system components. |
LO5 |
Design and implement a small system incorporating a datapath and datapath controller. |
LO6 |
Analyze systems specifications in order to plan, partition, design, implement and test a digital system. |
Dependencies |
Module Recommendations
This is prior learning (or a practical skill) that is recommended before enrolment in this module.
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No recommendations listed |
Co-requisite Modules
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No Co-requisite modules listed |
Additional Requisite Information
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No Co Requisites listed
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Indicative Content |
Datapaths:
Use a HDL to synthesize/simulate datapath elements (adders, multipliers, shift registers, ALU etc.), zero/sign extension, carry/overflow, casting (sign, size). Incorporating a pipeline (latency, throughput). Datapath controller – review of state machines. Development of a subsystem consisting of a datapath & datapath controller (eg. Shift and add multiplier, RPN calculator etc.)
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Memory:
FPGA memory resources (embedded memory & distributed logic cells). Use a HDL to synthesis/simulate RAM based components (single/dual port synchronous RAM, register file, Stack, FIFO). Use a HDL to synthesize/simulate systems that incorporate ROM (lookup-table, linearization, waveform generator). Memory initialization file.
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Clock:
Clock generation (PLL), management and distribution. Clock trees, clock skew, clock regions, power optimization. Clock enable & clock_division (used for synchronous clocking at very low frequency).
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System design:
Getting from a specification to system. Partitioning the system - block diagram, dataflow diagram, timing diagrams. Hardware/software co-design.
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CPU:
Overview of options for CPU - Softcore: (Microblaze, Nios, Cortex-M1, Risc-V). Hardcore (Cortex A series, Risc-V). Developing code for the embedded CPU of a selected SOC. Operating system (PetaLinux or UcLinux?).
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Buses:
Overview of SOC bus technologies (AMBA, AXI, CoreConnect, Wishbone). Use a chosen bus to interconnect system components (IP). Handshake, decoding, arbitration, clocking.
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Testbench:
Creating a self checking test bench. Layered testbench, scoreboarding, assertions, classes, constrained random variables.
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Systems issues:
Project - Development of a system that utilizes a CPU, Buses, IP and OS.
Investigate the implications of design approach/partitioning on power, speed, timing and area. Static timing analysis.
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Misc:
Automation of the build process using a script language such as Tcl/Tk.
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Module Content & Assessment
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Assessment Breakdown | % |
Continuous Assessment | 20.00% |
Project | 30.00% |
End of Module Formal Examination | 50.00% |
AssessmentsFull Time
End of Module Formal Examination |
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Reassessment Requirement |
Repeat examination
Reassessment of this module will consist of a repeat examination. It is possible that there will also be a requirement to be reassessed in a coursework element.
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SETU Carlow Campus reserves the right to alter the nature and timings of assessment
Module Workload
Workload: Full Time |
Workload Type |
Workload Category |
Contact Type |
Workload Description |
Frequency |
Average Weekly Learner Workload |
Hours |
Lecture |
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Contact |
No Description |
Every Week |
4.00 |
4 |
Laboratories |
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Contact |
No Description |
Every Week |
3.00 |
3 |
Independent Learning |
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Non Contact |
No Description |
Every Week |
5.00 |
5 |
Total Weekly Contact Hours |
7.00 |
Module Resources
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Recommended Book Resources |
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Pong P. Chu. (2018), FPGA Prototyping by SystemVerilog Examples, John Wiley & Sons, p.656, [ISBN: 9781119282662].
| Supplementary Book Resources |
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Louise H. Crockettet al. The Zynq Book, Strathclyde Academic Media, [ISBN: 9780992978709].
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Louise H Crockett et al. The Zynq Book Tutorials for Zybo and Zedboard, Strathclyde Academic Media, [ISBN: 9780992978730].
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Janick Bergeron. !!!Book Not FoundWriting Testbenches using SystemVerilog, Springer-Verlag, [ISBN: 9781441939784].
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Chris Spear,Greg Tumbush. (2012), SystemVerilog for Verification, Springer Science & Business Media, p.464, [ISBN: 9781461407140].
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Brown and Vranesic. Fundamentals of Digital Logic with Verilog Design, McGraw-Hill,, [ISBN: 9780071318716].
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Frank Bruno. (2021), FPGA Programming for Beginners, Packt Publishing, p.368, [ISBN: 9781789805413].
| This module does not have any article/paper resources |
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Other Resources |
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PetaLinux Tools Documentation, Xiinx,
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