Module Details

Module Code: DSGN C4601
Module Title: Microelectronic Design 1
Title: Microelectronic Design 1
Module Level:: 8
Credits:: 10
Module Coordinator: Cathal Nolan
Module Author:: Mark Norton
Domains:  
Module Description: To provide:
(a) Detailed analyses of semiconductor devices and their CAD models.
(b) Knowledge of circuit-level simulation and layout tools.
(c) Methodologies for digital and analogue IC analysis and design.
 
Learning Outcomes
On successful completion of this module the learner will be able to:
# Learning Outcome Description
LO1 Carry out a variety of simulations using a modern circuit simulator.
LO2 Derive and utilise semiconductor device models in circuit design simulations.
LO3 Layout and verify integrated circuit designs.
LO4 Design and analyse integrated amplifier circuits and cascodes.
LO5 Design and analyse current mirrors & reference circuits.
LO6 Design and analyse differential amplifiers.
Dependencies
Module Recommendations

This is prior learning (or a practical skill) that is recommended before enrolment in this module.
No recommendations listed
Co-requisite Modules
No Co-requisite modules listed
Additional Requisite Information
No Co Requisites listed
 
Indicative Content
1. Circuit Simulation & Layout
SPICE Device Elements; Semiconductor Devices; Analysis Modes and Techniques; Full-Custom IC Layout.
2. Semiconductor Fabrication
Wafer Preparation and Mask-making; Layering, Patterning and Doping; Electrical Tests and Die Packaging.
3. Semiconductor Device Modelling
Semiconductor Materials and their Properties; PN Junction and BJT Modelling; MOSFET Modelling; Amplifier Configurations.
4. Amplifier & Cascode Configurations
BJT & MOS integrated amplifiers; Cascoded transconductors and loads.
5. Current Mirrors & References
MOS and bipolar Current Mirroring; Temperature and Sensitivity Analysis; Voltage and Current Referencing.
6. Differential Amplifiers
Qualitative Analysis and Bipolar/MOSFET Differences; Small-Signal and Large-Signal Analysis; Cascode Differential Amplifiers; Common-Mode Rejection; Use of Active Loads.
Module Content & Assessment
Assessment Breakdown%
Continuous Assessment20.00%
Practical20.00%
End of Module Formal Examination60.00%

Assessments

Full Time

Continuous Assessment
Assessment Type Examination % of Total Mark 20
Timing n/a Learning Outcomes 2,4,5,6
Non-marked No
Assessment Description
Students will sit a written examination during the module.
No Project
Practical
Assessment Type Practical/Skills Evaluation % of Total Mark 20
Timing n/a Learning Outcomes 1,2,3,4,5,6
Non-marked No
Assessment Description
Students will complete a series of practical assignments, under supervision, using circuit simulation software.
End of Module Formal Examination
Assessment Type Formal Exam % of Total Mark 60
Timing End-of-Semester Learning Outcomes 1,2,3,4,5,6
Non-marked No
Assessment Description
A written examination, at the end of the module, will examine the extent of the student's achievement of the learning outcomes.
Reassessment Requirement
Repeat examination
Reassessment of this module will consist of a repeat examination. It is possible that there will also be a requirement to be reassessed in a coursework element.

SETU Carlow Campus reserves the right to alter the nature and timings of assessment

 

Module Workload

Workload: Full Time
Workload Type Workload Category Contact Type Workload Description Frequency Average Weekly Learner Workload Hours
Lecture Contact Lecture Every Week 4.00 4
Practicals Contact Practical Every Week 3.00 3
Independent Learning Time Non Contact No Description Every Week 3.00 3
Total Weekly Contact Hours 7.00
 
Module Resources
Recommended Book Resources
  • B. Razavi. (2013), Fundamentals of Microelectronics, 2nd ed.. Wiley, [ISBN: 978-111815632].
Supplementary Book Resources
  • R. Jacob Baker. (2019), CMOS: Circuit Design, Layout, and Simulation, 4th. Wiley-IEEE Press, p.1280, [ISBN: 978-111948151].
  • Behzad Razavi. (2017), Design Of Analog CMOS Integrated Circuits, 2nd. McGraw-Hill, [ISBN: 978-932598327].
  • R. Yanda, M. Heynes & A. Miller. (2005), Demystifying Chipmaking, Elsevier, p.280, [ISBN: 978-075067760].
This module does not have any article/paper resources
This module does not have any other resources
Discussion Note: