Module Details

Module Code: LANG C4601
Module Title: Hardware Description Language
Title: Hardware Description Language
Module Level:: 8
Credits:: 5
Module Coordinator: Cathal Nolan
Module Author:: Frank Fennelly
Domains:  
Module Description: To provide learners with the knowledge and skills needed to design, simulate, synthesis and validate a digital circuit using a contemporary hardware description language (HDL).
 
Learning Outcomes
On successful completion of this module the learner will be able to:
# Learning Outcome Description
LO1 Use a Hardware Description Language (HDL) to synthesize combinational and sequential logic.
LO2 Use a Hardware Description Language (HDL) to create a test bench to simulate and validate a small digital system which incorporates combinational and sequential logic
LO3 Design and implement a finite state machine (FSM) using a hardware description language (HDL).
LO4 Interface an FPGA to seven segment displays, Leds and mechanical switches (which are to be debounced).
Dependencies
Module Recommendations

This is prior learning (or a practical skill) that is recommended before enrolment in this module.
No recommendations listed
Co-requisite Modules
No Co-requisite modules listed
Additional Requisite Information
No Co Requisites listed
 
Indicative Content
Logic synthesis:
Logic synthesis using a MUX or LUT. Structure and operation of an FPGA.
Modelling techniques:
Gate-level, dataflow & behavioural modelling of digital systems. Combinational circuits – mux, decoder, priority encoder etc. Sequential circuits – registers, RAM, shift registers, counters etc Structural description of a hierarchical system. Synchronous design techniques.
HDL Language:
Lexical elements: comments, identifiers, numbers, strings etc. Data types: nets, registers, vectors, arrays. Operators, branching, looping etc. Procedural assignments: blocking and non-blocking. Sequential logic and event-based behaviour.
Finite state machine:
ASM charts, Moor & mealy machines, FSM encoding (one hot etc), HDL description of an FSM.
Design reuse:
Economic benefits of design reuse. Parameterized models. IP. Libraries. Supporting documentation and testbench.
Introduction to design verification:
Ethical and economic motivation for design verification. Develop a basic test bench for combinational circuits (adder) or sequential circuits (pre-settable up/down counter). Generating and assigning test vectors. Instance of design under test (DUT). Reporting test results. Tasks and functions.
Systems issues:
Implications of design techniques for power, speed, timing and area. Static timing analysis. Debouncing transient signals from switches etc
Module Content & Assessment
Assessment Breakdown%
Continuous Assessment50.00%
Project25.00%
Practical25.00%

Assessments

Full Time

Continuous Assessment
Assessment Type Case Studies % of Total Mark 50
Timing n/a Learning Outcomes 1,2,3
Non-marked No
Assessment Description
n/a
Project
Assessment Type Project % of Total Mark 25
Timing n/a Learning Outcomes 1,2,3,4
Non-marked No
Assessment Description
n/a
Practical
Assessment Type Practical/Skills Evaluation % of Total Mark 25
Timing n/a Learning Outcomes 1,2,3,4
Non-marked No
Assessment Description
n/a
No End of Module Formal Examination
Reassessment Requirement
Repeat examination
Reassessment of this module will consist of a repeat examination. It is possible that there will also be a requirement to be reassessed in a coursework element.

SETU Carlow Campus reserves the right to alter the nature and timings of assessment

 

Module Workload

Workload: Full Time
Workload Type Workload Category Contact Type Workload Description Frequency Average Weekly Learner Workload Hours
Lecture Contact No Description Every Week 3.00 3
Practicals Contact No Description Every Week 2.00 2
Independent Learning Non Contact No Description Every Week 3.00 3
Total Weekly Contact Hours 5.00
 
Module Resources
Supplementary Book Resources
  • Brent E. Nelson. Designing Digital Systems with SystemVerilog, 2. Independently published, [ISBN: 9781980926290].
  • Pong P. Chu. (2018), FPGA Prototyping by SystemVerilog Examples, John Wiley & Sons, p.656, [ISBN: 9781119282662].
  • Samir Palnitkar. (2003), Verilog HDL, Prentice Hall Professional, p.450, [ISBN: 9780130449115].
This module does not have any article/paper resources
This module does not have any other resources
Discussion Note: