Module Details

Module Code: SYST C4602
Module Title: Digital Systems
Title: Digital Systems
Module Level:: 8
Credits:: 10
Module Coordinator: Cathal Nolan
Module Author:: Frank Fennelly
Domains:  
Module Description: To provide learners with the knowledge and skills needed to design, simulate, synthesise and validate digital systems using SOC technology.
 
Learning Outcomes
On successful completion of this module the learner will be able to:
# Learning Outcome Description
LO1 Describe System on Chip (SoC) architectures and interfaces.
LO2 Use contemporary Electronic Design Automation (EDA) tools to develop digital systems using field programmable SOC devices.
LO3 Use a HDL to create a self-checking test bench to test a digital system which incorporates combinational and sequential logic.
LO4 To use a SOC bus technology to interconnect system components.
LO5 Design and implement a small system incorporating a datapath and datapath controller.
LO6 Analyze systems specifications in order to plan, partition, design, implement and test a digital system.
Dependencies
Module Recommendations

This is prior learning (or a practical skill) that is recommended before enrolment in this module.
No recommendations listed
Co-requisite Modules
No Co-requisite modules listed
Additional Requisite Information
No Co Requisites listed
 
Indicative Content
Datapaths:
Use a HDL to synthesize/simulate datapath elements (adders, multipliers, shift registers, ALU etc.), zero/sign extension, carry/overflow, casting (sign, size). Incorporating a pipeline (latency, throughput). Datapath controller – review of state machines. Development of a subsystem consisting of a datapath & datapath controller (eg. Shift and add multiplier, RPN calculator etc.)
Memory:
FPGA memory resources (embedded memory & distributed logic cells). Use a HDL to synthesis/simulate RAM based components (single/dual port synchronous RAM, register file, Stack, FIFO). Use a HDL to synthesize/simulate systems that incorporate ROM (lookup-table, linearization, waveform generator). Memory initialization file.
Clock:
Clock generation (PLL), management and distribution. Clock trees, clock skew, clock regions, power optimization. Clock enable & clock_division (used for synchronous clocking at very low frequency).
System design:
Getting from a specification to system. Partitioning the system - block diagram, dataflow diagram, timing diagrams. Hardware/software co-design.
CPU:
Overview of options for CPU - Softcore: (Microblaze, Nios, Cortex-M1, Risc-V). Hardcore (Cortex A series, Risc-V). Developing code for the embedded CPU of a selected SOC. Operating system (PetaLinux or UcLinux?).
Buses:
Overview of SOC bus technologies (AMBA, AXI, CoreConnect, Wishbone). Use a chosen bus to interconnect system components (IP). Handshake, decoding, arbitration, clocking.
Testbench:
Creating a self checking test bench. Layered testbench, scoreboarding, assertions, classes, constrained random variables.
Systems issues:
Project - Development of a system that utilizes a CPU, Buses, IP and OS. Investigate the implications of design approach/partitioning on power, speed, timing and area. Static timing analysis.
Misc:
Automation of the build process using a script language such as Tcl/Tk.
Module Content & Assessment
Assessment Breakdown%
Continuous Assessment20.00%
Project30.00%
End of Module Formal Examination50.00%

Assessments

Full Time

Continuous Assessment
Assessment Type Examination % of Total Mark 20
Timing n/a Learning Outcomes 1,2,3
Non-marked No
Assessment Description
n/a
Project
Assessment Type Project % of Total Mark 30
Timing n/a Learning Outcomes 2,3,4,5,6
Non-marked No
Assessment Description
n/a
No Practical
End of Module Formal Examination
Assessment Type Formal Exam % of Total Mark 50
Timing End-of-Semester Learning Outcomes 1,2,3,5
Non-marked No
Assessment Description
n/a
Reassessment Requirement
Repeat examination
Reassessment of this module will consist of a repeat examination. It is possible that there will also be a requirement to be reassessed in a coursework element.

SETU Carlow Campus reserves the right to alter the nature and timings of assessment

 

Module Workload

Workload: Full Time
Workload Type Workload Category Contact Type Workload Description Frequency Average Weekly Learner Workload Hours
Lecture Contact No Description Every Week 4.00 4
Laboratories Contact No Description Every Week 3.00 3
Independent Learning Non Contact No Description Every Week 5.00 5
Total Weekly Contact Hours 7.00
 
Module Resources
Recommended Book Resources
  • Pong P. Chu. (2018), FPGA Prototyping by SystemVerilog Examples, John Wiley & Sons, p.656, [ISBN: 9781119282662].
Supplementary Book Resources
  • Louise H. Crockettet al. The Zynq Book, Strathclyde Academic Media, [ISBN: 9780992978709].
  • Louise H Crockett et al. The Zynq Book Tutorials for Zybo and Zedboard, Strathclyde Academic Media, [ISBN: 9780992978730].
  • Janick Bergeron. !!!Book Not FoundWriting Testbenches using SystemVerilog, Springer-Verlag, [ISBN: 9781441939784].
  • Chris Spear,Greg Tumbush. (2012), SystemVerilog for Verification, Springer Science & Business Media, p.464, [ISBN: 9781461407140].
  • Brown and Vranesic. Fundamentals of Digital Logic with Verilog Design, McGraw-Hill,, [ISBN: 9780071318716].
  • Frank Bruno. (2021), FPGA Programming for Beginners, Packt Publishing, p.368, [ISBN: 9781789805413].
This module does not have any article/paper resources
Other Resources
Discussion Note: